Programmable logic devices (PLDs), such as field programmable gate arrays, are frequently used in microprocessor-based systems. The advantages of PLDs include design flexibility and improved time-to-market for products, since large groups of discrete logic components and the connections between them can be replaced by a single integrated circuit. Hardware platforms can be finalized early in the design process and product enhancements may be implemented by changing the programming of the PLD.
A trade-off, however, is that field programmable logic devices may be implemented using volatile interconnections, including RAM-based architectures. As such, the PLD may need to be reprogrammed after a system restart or power-up, typically during a system initialization procedure. In many hardware systems, it is desirable to ensure that the system is configured and operational as quickly as possible. This is especially true in telecommunications systems where the time to restart a failing system equates to the time a service is unavailable. Moreover, regulations or industry standards may establish a maximum restart time that must be met.
In embedded systems, the microprocessor often bears the burden of programming all programmable logic devices in addition to initializing other hardware and software as part of a system initialization routine.
In general, PLDs may be programmed by transferring a bit stream of programming data using either a serial or parallel mode. The PLD decodes the bit stream and configures its internal logic accordingly. In the serial mode, data and clock signals may be produced by the microprocessor to provide programming data to the PLD. This technique, known as “bit-banging,” may be implemented using a general purpose I/O port of the microprocessor and requires the microprocessor to toggle the value of a bit in the associated port register to produce the clock signal, which may prevent the microprocessor from performing other tasks. In parallel mode, the PLD may be programmed by writing data to the PLD using the microprocessor's address and data bus. Although more efficient than serial programming, I/O pins used by the PLD to connect to the address and data bus remain connected to the bus after programming, which may not be desirable in some architectures. In addition, direct access to address and data busses may not be possible in some architectures.
Accordingly, there is a need in the art to provide a method and system for programming PLDs in an embedded microprocessor system that efficiently uses microprocessor resources.